Difference between revisions of "Reconfigurable Computing"
From esoterum.org
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:-UWisconsin, Madison | :-UWisconsin, Madison | ||
*M. Vuletic, L. Pozzi, P. Ienne, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/9306/29574/01342483.pdf?tp=&arnumber=1342483&isnumber=29574 "Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing"], 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Page(s):339 - 351 | *M. Vuletic, L. Pozzi, P. Ienne, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/9306/29574/01342483.pdf?tp=&arnumber=1342483&isnumber=29574 "Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing"], 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Page(s):339 - 351 | ||
| + | :-Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory | ||
=== Adaptive Algorithm for Hardware Reconfiguration === | === Adaptive Algorithm for Hardware Reconfiguration === | ||
Revision as of 14:40, 14 January 2008
RC: reconfigurable computing HPRC: high performance reconfigurable computing RH: reconfigurable hardware
Papers
- R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
- -UMass, Amherst
- R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: A Survey", Journal of VLSI Signal Processing, May/June 2001, pp. 7-27
- -UMass, Amherst
- (5.1) Wenyin Fu, Katherine Compton, "A Simulation Platform for Reconfigurable Computing Research", Field Programmable Logic and Applications, 2006. FPL '06. International Conference on 28-30 Aug. 2006 Page(s):1 - 7
- -UWisconsin, Madison
- M. Vuletic, L. Pozzi, P. Ienne, "Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing", 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Page(s):339 - 351
- -Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
Adaptive Algorithm for Hardware Reconfiguration
- Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson, "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder", IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488
- -UMass, Amherst
Last printed: 5.1
