Difference between revisions of "H.264 and Reconfigurable Architecture"
From esoterum.org
| Line 1: | Line 1: | ||
*Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, [http://chongjike.net/DrupalFiles/ICME2007.pdf Efficient Parallelization of H.264 Decoding With Macro Block Level Scheduling], Multimedia and Expo, 2007 IEEE International Conference on, 1874-1877, July, 2007. | *Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, [http://chongjike.net/DrupalFiles/ICME2007.pdf Efficient Parallelization of H.264 Decoding With Macro Block Level Scheduling], Multimedia and Expo, 2007 IEEE International Conference on, 1874-1877, July, 2007. | ||
:-EECS Department, University of California, Berkeley, USA | :-EECS Department, University of California, Berkeley, USA | ||
| − | :*[9] Im Yong Lee, Il-Hyun Park, Dong-Wook Lee, and Ki-Young Choi, [http://www.altera.com/literature/dc/1.5-2005_Korea_2nd_SeoulNational-web.pdf Implementation of the H.264/AVC Decoder Using the Nios II Processor], Nios® II Embedded Processor Design Contest, 2005 | + | :*[9] Im Yong Lee, Il-Hyun Park, Dong-Wook Lee, and Ki-Young Choi, [http://www.altera.com/literature/dc/1.5-2005_Korea_2nd_SeoulNational-web.pdf Implementation of the H.264/AVC Decoder Using the Nios II Processor], Altera Nios® II Embedded Processor Design Contest, 2005 |
::-Institution: Seoul National University | ::-Institution: Seoul National University | ||
:*[10] Erik B. van der Tol, ; Egbert G. Jaspers, ; Rob H. Gelderblom, [http://vca.ele.tue.nl/publications/data/Jaspers2003a.pdf Mapping of H.264 decoding on a multiprocessor architecture], Image and Video Communications and Processing 2003. Edited by Vasudev, Bhaskaran; Hsing, T. Russell; Tescher, Andrew G.; Ebrahimi, Touradj. Proceedings of the SPIE, Volume 5022, pp. 707-718 (2003). | :*[10] Erik B. van der Tol, ; Egbert G. Jaspers, ; Rob H. Gelderblom, [http://vca.ele.tue.nl/publications/data/Jaspers2003a.pdf Mapping of H.264 decoding on a multiprocessor architecture], Image and Video Communications and Processing 2003. Edited by Vasudev, Bhaskaran; Hsing, T. Russell; Tescher, Andrew G.; Ebrahimi, Touradj. Proceedings of the SPIE, Volume 5022, pp. 707-718 (2003). | ||
Revision as of 17:57, 3 June 2008
- Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, Efficient Parallelization of H.264 Decoding With Macro Block Level Scheduling, Multimedia and Expo, 2007 IEEE International Conference on, 1874-1877, July, 2007.
- -EECS Department, University of California, Berkeley, USA
- [9] Im Yong Lee, Il-Hyun Park, Dong-Wook Lee, and Ki-Young Choi, Implementation of the H.264/AVC Decoder Using the Nios II Processor, Altera Nios® II Embedded Processor Design Contest, 2005
- -Institution: Seoul National University
- [10] Erik B. van der Tol, ; Egbert G. Jaspers, ; Rob H. Gelderblom, Mapping of H.264 decoding on a multiprocessor architecture, Image and Video Communications and Processing 2003. Edited by Vasudev, Bhaskaran; Hsing, T. Russell; Tescher, Andrew G.; Ebrahimi, Touradj. Proceedings of the SPIE, Volume 5022, pp. 707-718 (2003).
- Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo, PeaCE: A hardware-software codesign environment for multimedia embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES) Volume 12 , Issue 3 (August 2007)
- -Seoul National University, Seoul, Korea
