Difference between revisions of "CSE591 Low Power Architecture"
From esoterum.org
| Line 37: | Line 37: | ||
*[http://www.intel.com/technology/magazine/research/power-efficiency-0206.htm Intel article on EPI throttling] | *[http://www.intel.com/technology/magazine/research/power-efficiency-0206.htm Intel article on EPI throttling] | ||
*[http://www.iccd-conference.org/proceedings/2004/22310236.pdf Best of Both Latency and Throughput (introduces EPI Throttling)] | *[http://www.iccd-conference.org/proceedings/2004/22310236.pdf Best of Both Latency and Throughput (introduces EPI Throttling)] | ||
| + | |||
| + | === Vocabulary === | ||
| + | |||
| + | [http://en.wikipedia.org/wiki/Wall_clock_time Wall clock time] | ||
Revision as of 23:50, 17 February 2007
Contents
29 Jan 07 Presentation I
Instruction Level Power Dissipation in the Intel XScale Embedded Microprocessor
Tools for power analysis of microprocessors at the microarchitectural level:
- This software is based on the SimpleScalar software
- Download Wattch
5 Feb 07 Project I Topic due
12 Feb 07 Project I due
Simulation Software
DVFS Project Resources
- Concise references for DVFS project from 2003 using speedstep on an IBM Thinkpad
- Good linux kernel reference
Project II
- XScale project using
PXA25080200 already in Dr. Shrivastava's possession.
19 Feb 07 Presentation II
- -Energy Efficient Co-Adaptive Instruction Fetch and Issue (Throttling paper)
- -Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors (Throttling paper)
- Amdahl's Law (Wikipedia)
- Intel article on EPI throttling
- Best of Both Latency and Throughput (introduces EPI Throttling)
