Difference between revisions of "EEE525 VLSI Design"
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=== Virtuoso === | === Virtuoso === | ||
*[http://bwrc.eecs.berkeley.edu/Classes/Icdesign/ee141_f03/CadenceLabs/Lab2/VirtuosoTutorial.htm Layout tutorial from Berkeley] | *[http://bwrc.eecs.berkeley.edu/Classes/Icdesign/ee141_f03/CadenceLabs/Lab2/VirtuosoTutorial.htm Layout tutorial from Berkeley] | ||
+ | *To add labels and pin names etc., they have to be attached to a geometry, which means a wire net. To add a label such as “INV M12” where “M12” is a specific transistor in the schematic, using the “add label” button on the left, Select The Text Layer first, then open the label window, check the “Attach” checkbox, and after the label is placed, you have a connector attached to the mouse from the label which needs to be placed on a wire or it won’t pass DRC. Adding this kind of label probably also names the wire net, so I'm sure that there will be problems later if | ||
=== Tutorials === | === Tutorials === |
Revision as of 11:27, 23 April 2008
Contents
Project
Digital Design
- Cmos Logic Circuit Design By John P. Uyemura (Google online)
- -3.1.1 (p.106) Thorough treatment of Inverter VTC, calculating VIL and VIH
Homework 2
- prob. 2. Tutorial problems with answers from MIT
- prob. 2. Voltage Transfer Characteristics from Berkeley
Homework 3
- parasitic probe?
- Tutorial from MIT, calculating avg/integral
More Cadence Tutorials
- Cadence Tools Tutorial from beginning to automatically generated counter layout
- Full-Custom Design with Cadence - Tutorial, Graz
Cadence
- Configuration path:
/usr/local/cadence2/NCSU
- vlsi2.eas.asu.edu information
- VLSI Readme, with Cadence instructions
- > vlsi2 Read-me file
Virtuoso
- Layout tutorial from Berkeley
- To add labels and pin names etc., they have to be attached to a geometry, which means a wire net. To add a label such as “INV M12” where “M12” is a specific transistor in the schematic, using the “add label” button on the left, Select The Text Layer first, then open the label window, check the “Attach” checkbox, and after the label is placed, you have a connector attached to the mouse from the label which needs to be placed on a wire or it won’t pass DRC. Adding this kind of label probably also names the wire net, so I'm sure that there will be problems later if
Tutorials
- >> Advanced calculator tutorial from MIT
- > Advanced tutorial from UCLA
- > UWaterloo Tutorial, thorough on parametric analysis with some pPar information
- > Tutorial at UPenn
- > Lab Tutorial at UPenn
- > Tutorial at WPI
- > Tutorial at USC, Ppar variable information
- > Cadence Manual at NMSU
- Tutorial, VLSI
- Tutorial on Virtuoso Schematic editor from OSU, layout with ALU
- Berkeley Virtuoso tutorial
- Cadence FAQ
- NCSU CDK User FAQ
- Circuit simulation using Spectre (UT Dallas)
- Unlocking files
- -At the shell prompt, type
clsAdminTool
, you'll get a>
prompt. - -Type
ale /afs/asu.edu/users/m/b/a/mbaker7/cadence/EE525
(using the correct path to your library). You should get a list of existing locks in that library. - -There are two ways to release the lock in question:
- To release all the locks in the library, type
are /full/path/to/your/library/directory
- To release the lock on a particular file, type
asre /full/path/to/the/locked/file
- To release all the locks in the library, type
- -Type
quit
orexit
.
Spectre
Design Rules
Spectre
- Model Libraries:
- /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dN.m
- /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dP.m