Difference between revisions of "Cell Broadband Engine"

Revision as of 16:22, 12 June 2008

Motivation for SDR implementation: What makes the IBM Cell a good candidate for an SDR implementation?

• Can we get the power low enough for the processor to be feasible for handheld devices?
• Does context switching give us an advantage?

IBM

• The Cell project at IBM
• Cell programming projects
• IBM Cell reference documentation
• Power.org CBE development resources

Training

• Training Series targeted for IBM employees
• Power Architecture recommended reading

Programming

• Installing Yellowdog Linux on PS3
• Programming high-performance applications on the Cell BE processor, Part 1: An introduction to Linux on the PLAYSTATION 3
• Programming high-performance applications on the Cell BE processor, Part 2: Program the synergistic processing elements of the Sony PLAYSTATION 3
• Programming high-performance applications on the Cell BE processor, Part 3: Meet the synergistic processing unit
• Programming high-performance applications on the Cell BE processor, Part 4: Program the SPU for performance
• Programming high-performance applications on the Cell BE processor, Part 5: Programming the SPU in C/C++
• Programming high-performance applications on the Cell/B.E. processor, Part 6: Smart buffer management with DMA transfers

Software/Development

• IBM Cell SDK Downloads
• "Linux patches, tools support Cell Processor evaluation"
• Debugging Cell Broadband Engine systems Essential tools and techniques for the Cell BE software developer
• Matrix Inverse Application
• MPI microtask for programming the Cell Broadband Engine processor
• A Programming Example: Large FFT on the Cell Broadband Engine

Hardware

• IBM BladeCenter QS20, Server implementing Cell Broadband Architecture

Articles

• IEEE Search on Cell Processor
• External papers from the IBM web site

General/Architecture

• > (2.1) D.C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, P.M. Harvey, H.P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D.L. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, K. Yazawa, "Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor", Technol. Group, IBM Syst., Austin, TX, USA, IEEE Journal of Solid-State Circuits, Volume: 41 , Issue: 1, pp. 179-196, Jan. 2006 (originally forwarded by Dr. Chatha)
• CODES+ISSS 2007 Tutorial summary on Cell Processor
• Kahle, J., "The Cell Processor Architecture", IBM, MICRO-38. 38th Annual IEEE/ACM International Symposium on Microarchitecture, 12-16 Nov. 2005
• M. Day, P. Hofstee, "Hardware and software architectures for the CELL processor", IBM Systems&Technology Group, Austin, TX, Hardware/Software Codesign and System Synthesis, CODES+ISSS, Sept. 2005
• D. Stasiak, R. Chaudhry, D. Cox, S. Posluszny, J. Warnock, S. Weitzel, D. Wendel, M. Wang, "Cell processor low-power design methodology" Syst. & Technol. Group, IBM Corp., Austin, TX, USA, Micro, IEEE, Volume: 25 , Issue: 6 pp. 71-78, Nov.-Dec. 2005
• Tom Krazit, "IBM, Sony, Toshiba Unveil Nine-Core Cell Processor", IDG News Service, February 07, 2005

-"Cell will probably consume around 30 watts of power, similar to the Emotion Engine processor in the PlayStation 2"

• (2.4) A. E. Eichenberger, K. O’Brien, K. O’Brien, P. Wu, T. Chen, Pe. H. Oden, D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao, M. Gschwind, "Optimizing Compiler for a CELL Processor", Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, 2005
• David Krolak, "Just like being there: Papers from the Fall Processor Forum 2005: Unleashing the Cell Broadband Engine Processor: The Element Interconnect Bus", IBM, 29 Nov 2005

High Performance Computing Application

• > (2.2) A. Buttari, P. Luszczek, J. Kurzak, J. Dongarra, G. Bosilca, "A Rough Guide to Scientific Computing On the PlayStation 3", Technical Report UT-CS-07-595, Innovative Computing Laboratory, University of Tennessee Knoxville, May 11, 2007
• "Researchers Analyze HPC Potential of Cell Processor", HPC Wire, May 2006

-S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, K. Yelick, "The Potential of the Cell Processor for Scientific Computing", ACM, May 2006

• D. A. Bader, V. Agarwal, K. Madduri, "On the Design and Analysis of Irregular Algorithms on the Cell Processor: A Case Study of List Ranking", IEEE, 2007
• David A. Bader, Virat Agarwal, "BFFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine", High Performance Computing – HiPC 2007, pp. 172-184, 2007
• S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, K. Yelick, Scientific Computing Kernels on the Cell Processor, International Journal of Parallel Programming, 2007

Media Application

• (2.3) L. Liu, Q. Liu, A. Natsev, K. A. Ross, J. R. Smith, A. L. Varbanescu, "Digital Media Indexing on the Cell Processor", ICME, 2007
• The Cell BE Processor: A Broadband Engine for Broadcast Applications
• N. Kato, K. Takeuchi, S. Maeda, M. Shimbayashi, R. Sakai, H. Nozue, J. Amemiya, Digital Media Applications on A CELL Software Platform, Toshiba Corporation, IEEE, 2006
• (2.5) Nobuhiro KATO, Kazuaki TAKEUCHI, Seiji MAEDA, Mitsuru SHIMBAYASHI, Ryuji SAKAI, Hiroshi NOZUE and Jiro AMEMIYA, Digital Media Applications on A CELL Software Platform, International Conference on Consumer Electronics, 2006. ICCE '06. 2006 Digest of Technical Papers. 7-11 Jan. 2006 Page(s):347 - 348

-TOSHIBA Corporation, JAPAN

• (2.6) Ashish Jagmohan, Brent Paulovicks, Vadim Sheinin, Hangu Yeo, H.264 Video Encoding Algorithm on Cell Broadband Engine, Department of Multimedia Technologies, IBM TJ Watson Research

Real Time Application

• S. Maeda, S. Asano, T. Shimada, K. Awazu, H. Tago, "A real-time software platform for the Cell processor", Toshiba Corp., Japan, Micro, IEEE, Volume: 25 , Issue: 5, pp. 20-29, Sept.-Oct. 2005
• Seiji Maeda, Sigehiro Asano, Tomofumi Shimada, Koichi Awazu, Haruyuki Tago, "A Real-Time Software Platform for the Cell Processor", IEEE, 2005

Other Applications

• Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Last printed: 2.6