Difference between revisions of "DVFS"
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*[http://www.arm.com/pdfs/Intrinsyc_IEM_Benchmarking_for_WinCE.pdf "Intelligent Energy Manager (IEM) Benchmarking on a Freescale’s iMX31 Multimedia Processor"], SEP 2006 | *[http://www.arm.com/pdfs/Intrinsyc_IEM_Benchmarking_for_WinCE.pdf "Intelligent Energy Manager (IEM) Benchmarking on a Freescale’s iMX31 Multimedia Processor"], SEP 2006 | ||
*[http://www.csl.cornell.edu/~lijian/docs/lij_power_hpca06.pdf "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors"] | *[http://www.csl.cornell.edu/~lijian/docs/lij_power_hpca06.pdf "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors"] | ||
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| + | *Li, J.; Martinez, J.F.; , [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1598114&tag=1 Dynamic power-performance adaptation of parallel computation on chip multiprocessors]. High-Performance Computer Architecture, 2006. The Twelfth International Symposium on , vol., no., pp. 77- 87, 11-15 Feb. 2006 | ||
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*M. Pedram, K. Choi, R. Soma, [http://ieeexplore.ieee.org/iel5/43/30006/01372658.pdf "Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Tradeoff Based on the Ratio of Off-Chip Access to On-Chip Computation Times"] | *M. Pedram, K. Choi, R. Soma, [http://ieeexplore.ieee.org/iel5/43/30006/01372658.pdf "Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Tradeoff Based on the Ratio of Off-Chip Access to On-Chip Computation Times"] | ||
*[http://systems.cs.colorado.edu/EnergyEfficientComputing/os_power_computing.htm "DVFS information from the University of Colorado"] | *[http://systems.cs.colorado.edu/EnergyEfficientComputing/os_power_computing.htm "DVFS information from the University of Colorado"] | ||
Revision as of 00:55, 10 September 2010
DVFS, Wikipedia An article that need to be written.
Contents
Video Decoding
- Mesarina, M. and Turner, Y. 2003. Reduced energy decoding of MPEG streams. Multimedia Syst. 9, 2 (Aug. 2003), 202-213.
- Lee, B., Nurvitadhi, E., Dixit, R., Yu, C., and Kim, M. 2005. Dynamic voltage scaling techniques for power efficient video decoding. J. Syst. Archit. 51, 10-11 (Oct. 2005), 633-652.
- Pouwelse, J., Langendoen, K., and Sips, H. 2001. Dynamic voltage scaling on a low-power microprocessor. In Proceedings of the 7th Annual international Conference on Mobile Computing and Networking (Rome, Italy). MobiCom '01. ACM, New York, NY, 251-259.
Switching Overhead
- Johan De Gelas. Dynamic Power Management: A Quantitative Approach. Online: AnandTech.com. January 18, 2010.
- -Xeon C-state transition times
- -P-state frequency example, (10 133MHz steps from 1.2GHz to 2.53Ghz)
- -"On dual-core Athlon X2 and Phenom I, it was for example impossible to use DVFS and get decent HD-video decoding. There are three important performance problems with dynamic power management:
- Transitioning from one P-state to another takes a while, especially if you scale up. Active cores will probe idle or lower P-state cores quite frequently. The OS power manager has to predict whether or not the process will need more processing power soon or not. As a result the OS transitions a lot slower than the hardware."
- Intel Xeon Processor 5600 Series, Datasheet Volume I. March 2010.
- -p. 168: "Processor core (including shared cache) is unavailable for less than 2us during the frequency transition."
- Power consumption table for 5600 by C-state
- -p. 167: "Processor C-State Power Specifications" table power consumption by C-state
- Adrian Hoban. Designing Real-Time Solutions on Embedded Intel® Architecture Processors. Intel Corporation. May, 2010.
- Power consumption table for several processors at different power management C-states
- Taylor Kidd. There's got to be a catch. Intel Software Blog. April 29, 2008 at 9:24 am
- -20us transition overhead for all C-states?
- Advanced Configuration and Power Interface Specification. Hewlett-Packard, Intel, Microsoft, Toshiba Corporations, and Phoenix Technologies Ltd. Revision 4.0a. April 5, 2010
- Power Efficiency – Analysis and SW Development Recommendations for Intel® Atom™ based MID platforms. Intel Software Network. May 4, 2009 9:00 PM PDT.
- -Overview charts on C-State configuration details wakeup times and power consumption
- -Gives wakeup times, but don't know where they came from
- -example power performance by P-states
- Power states overview slides from University of Pittsburg, example of c-state selections over time
DVFS Project Resources
- Concise references for DVFS project from 2003 using speedstep on an IBM Thinkpad
- Good linux kernel reference
- Topic: Addressing the power cost of switching overhead in DVFS processors.
Experimental Setup
DVFS Papers
- Burd, T.; Pering, T.; Stratakos, A.; Brodersen, R.; , A dynamic voltage scaled microprocessor system. Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International , vol., no., pp.294-295, 466, 2000.
- Isci, Martonosi, Buyuktosunoglu, "Long-term Workload Phases: Duration Predictions and Applications to DVFS
- Prediction and switching overhead
- "The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms", 1998
- "Intelligent Energy Manager (IEM) Benchmarking on a Freescale’s iMX31 Multimedia Processor", SEP 2006
- "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors"
- Li, J.; Martinez, J.F.; , Dynamic power-performance adaptation of parallel computation on chip multiprocessors. High-Performance Computer Architecture, 2006. The Twelfth International Symposium on , vol., no., pp. 77- 87, 11-15 Feb. 2006
- M. Pedram, K. Choi, R. Soma, "Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Tradeoff Based on the Ratio of Off-Chip Access to On-Chip Computation Times"
- "DVFS information from the University of Colorado"
- Zhu, Mueller, "Feedback EDF Scheduling Exploiting Hardware-Assisted Asynchronous Dynamic Voltage Scaling, North Carolina State University"
