H.264 and Reconfigurable Architecture
From esoterum.org
- (6.2) Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, Efficient Parallelization of H.264 Decoding With Macro Block Level Scheduling, Multimedia and Expo, 2007 IEEE International Conference on, 1874-1877, July, 2007.
- -EECS Department, University of California, Berkeley, USA
- (6.4) [9] Im Yong Lee, Il-Hyun Park, Dong-Wook Lee, and Ki-Young Choi, Implementation of the H.264/AVC Decoder Using the Nios II Processor, Altera Nios® II Embedded Processor Design Contest, 2005
- -Institution: Seoul National University
- (6.3) [10] Erik B. van der Tol, ; Egbert G. Jaspers, ; Rob H. Gelderblom, Mapping of H.264 decoding on a multiprocessor architecture, Image and Video Communications and Processing 2003. Edited by Vasudev, Bhaskaran; Hsing, T. Russell; Tescher, Andrew G.; Ebrahimi, Touradj. Proceedings of the SPIE, Volume 5022, pp. 707-718 (2003).
- (6.1) Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo, PeaCE: A hardware-software codesign environment for multimedia embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES) Volume 12 , Issue 3 (August 2007)
- -Seoul National University, Seoul, Korea
Last printed: 6.4
