Coarse Grained Reconfigurable Architectures
26. Mapping applications to an FPFA tile [field programmable function array] Rosien, M.A.J.; Yuanqing Guo; Smit, G.J.M.; Krol, T.; Design, Automation and Test in Europe Conference and Exhibition, 2003 2003 Page(s):1124 - 1125 Digital Object Identifier 10.1109/DATE.2003.1253764
Summary: This paper introduces a transformational design method which can be used to map code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a control data flow graph (C.....
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27. A decade of reconfigurable computing: a visionary retrospective
Hartenstein, R.; Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings 13-16 March 2001 Page(s):642 - 649 Digital Object Identifier 10.1109/DATE.2001.915091
Summary: The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm t.....
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28. KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures
Hartenstein, R.; Herz, M.; Hoffmann, T.; Nageldinger, U.; Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific 25-28 Jan. 2000 Page(s):163 - 168 Digital Object Identifier 10.1109/ASPDAC.2000.835089
Summary: This paper introduces a CAD environment for design-space exploration of coarse grain reconfigurable KressArray architectures and similar platforms, To find an optimal solution to a given application domain this KressArray Xplorer supports experimenti.....
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29. Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors
Taniguchi, I.; Jayapala, M.; Raghavan, P.; Catthoor, F.; Sakanushi, K.; Takeuchi, Y.; Imai, M.; Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific 19-22 Jan. 2009 Page(s):449 - 454 Digital Object Identifier 10.1109/ASPDAC.2009.4796521
Summary: Systematic architecture exploration from vast solution space is a complex problem in embedded system design. It is very difficult to explore a best architecture fast and accurately because accurate evaluation usually consumes significant amount of ti.....
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30. Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study
Chase, J.; Nelson, B.; Bodily, J.; Zhaoyi Wei; Dah-Jye Lee; Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on 14-15 April 2008 Page(s):173 - 182 Digital Object Identifier 10.1109/FCCM.2008.24
Summary: FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing a variety of computations. Applications successfully implemented on FPGAs have typically contained high levels of parallelism and have of.....
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31. Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
Davila, J.; de Torres, A.; Sanchez, J.M.; Sanchez-Elez, M.; Bagherzadeh, N.; Rivera, F.; Design, Automation and Test in Europe, 2006. DATE '06. Proceedings Volume 2, 6-10 March 2006 Page(s):6 pp. Digital Object Identifier 10.1109/DATE.2006.243748
Summary: In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computational and has an important restriction in execution time due to the req.....
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32. Design space exploration for low-power reconfigurable fabrics
Mehta, G.; Hoare, R.R.; Stander, J.; Jones, A.K.; Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International 25-29 April 2006 Page(s):4 pp. Digital Object Identifier 10.1109/IPDPS.2006.1639484
Summary: This paper presents a parameterizable, coarse grained, reconfigurable fabric model that attempts to maintain field programmable gate array (FPGA)-like programmability and computer aided design (CAD), with application specific integrated circuit (ASIC.....
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33. A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation
Verma, R.; Akoglu, A.; Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on 14-18 April 2008 Page(s):1 - 8 Digital Object Identifier 10.1109/IPDPS.2008.4536528
Summary: This paper proposes a novel application-specific hybrid coarsegrained reconfigurable architecture with a flexible network on chip (NoC) mechanism. Architecture supports variable block size motion estimation (VBSME) with much less resources than ASIC .....
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34. Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme
Xydis, S.; Economakos, G.; Pekmestzi, K.; Embedded Computer Systems: Architectures, Modeling and Simulation, 2007. IC-SAMOS 2007. International Conference on 16-19 July 2007 Page(s):137 - 144 Digital Object Identifier 10.1109/ICSAMOS.2007.4285744
Summary: This paper presents a design technique for coarse grained reconfigurable cores targeting mostly DSP applications. The proposed technique inlines flexibility into custom carry-save-arithmetic (CSA) datapaths exploiting a stable and canonical interconn.....
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35. A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template
Hatanaka, A.; Bagherzadeh, N.; Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International 26-30 March 2007 Page(s):1 - 8 Digital Object Identifier 10.1109/IPDPS.2007.370371
Summary: Coarse grain reconfigurable arrays (CGRAs) have been drawing attention due to its programmability and performance. Compilation onto CGRAs is still an open problem. Several groups have proposed algorithms that software pipeline loops onto CGRAs. In th.....
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36. Instruction-Set Extension for Cryptographic Applications on Reconfigurable Platform
Majzoub, S.; Diab, H.; System-on-Chip for Real-Time Applications, The 6th International Workshop on Dec. 2006 Page(s):173 - 178 Digital Object Identifier 10.1109/IWSOC.2006.348231
Summary: Recently, the area of reconfigurable computing has received considerable interest. Reconfigurable system is a specific name that is used for any machine that can be reconfigured during runtime to execute an algorithm as a hardware circuit. As a middl.....
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37. Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
Hasegawa, Y.; Abe, S.; Kurotaki, S.; Vu Manh Tuan; Katsura, N.; Nakamura, T.; Nishimura, T.; Amano, H.; Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International 25-29 April 2006 Page(s):8 pp. Digital Object Identifier 10.1109/IPDPS.2006.1639431
Summary: Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed.....
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38. Evaluation strategies for coarse grained reconfigurable architectures
Lange, H.; Schroder, H.; Field Programmable Logic and Applications, 2005. International Conference on 24-26 Aug. 2005 Page(s):586 - 589 Digital Object Identifier 10.1109/FPL.2005.1515791
Summary: The granularity of a reconfigurable architecture has a big impact on important properties such as output data rate, area and energy consumption. Fine-grained architectures such as SRAM-based FPGAs provide good flexibility and speed, but they suffer f.....
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39. Stream applications on the dynamically reconfigurable processor
Suzuki, M.; Hasegawa, Y.; Yamada, Y.; Kaneko, N.; Deguchi, K.; Amano, H.; Anjo, K.; Motomura, M.; Wakabayashi, K.; Toi, T.; Awashima, T.; Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on 2004 Page(s):137 - 144 Digital Object Identifier 10.1109/FPT.2004.1393261
Summary: Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on on.....
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40. A framework for reconfigurable computing: task scheduling and context management
Maestre, R.; Kurdahi, F.J.; Fernandez, M.; Hermida, R.; Bagherzadeh, N.; Singh, H.; Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 9, Issue 6, Dec. 2001 Page(s):858 - 873 Digital Object Identifier 10.1109/92.974899
Summary: Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the de.....
AbstractPlus | Full Text: PDF(387 KB) IEEE JNL
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41. Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms
Ma, F.; Knight, J.P.; Plett, C.; Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 13, Issue 5, May 2005 Page(s):553 - 563 Digital Object Identifier 10.1109/TVLSI.2005.844286
Summary: One of the challenges of designing for coarse-grain reconfigurable arrays is the need for mature tools. This is especially important because of the heterogeneity of the larger, more predefined (and hence more specialized) array elements. This work de.....
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42. Dynamically Mapping N-Point IDCT on Coarse-Grained Reconfigurable Platform CTaiJi
Liguo Song; Future Generation Communication and Networking Symposia, 2008. FGCNS '08. Second International Conference on Volume 3, 13-15 Dec. 2008 Page(s):99 - 102 Digital Object Identifier 10.1109/FGCNS.2008.25
Summary: The area of reconfigurable computing platform is consolidating itself as a bridge between application specific integrated circuit 1(ASIC) and general-purpose processors. There are two types of reconfiguration(dynamic and static). Dynamic reconfigurat.....
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43. Finite Domain Constraints Based Delay Aware Placement Tool for FPOAs
Saraswat, R.; Eames, B.; Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on 3-5 Dec. 2008 Page(s):145 - 150 Digital Object Identifier 10.1109/ReConFig.2008.50
Summary: FPOAs are reconfigurable devices similar to FPGAs but offer a much higher level of abstraction than the gate level. The main advantage of FPOAs is their deterministic on chip network, which guarantees that an application executes at the design freque.....
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44. Performance improvements using coarse-grain reconfigurable logic in embedded SOCs
Dimitroulakos, G.; Galanis, M.D.; Goutis, C.E.; Field Programmable Logic and Applications, 2005. International Conference on 24-26 Aug. 2005 Page(s):630 - 635 Digital Object Identifier 10.1109/FPL.2005.1515801
Summary: A hardware/software partitioning methodology for improving applications' performance in embedded single-chip systems is presented. Critical software parts are accelerated on hardware of a system comprised by an embedded processor and coarse-grain rec.....
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45. When reconfigurable architecture meets network-on-chip
Soares, R.; Silva, I.S.; Azevedo, A.; Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on 7-11 Sept. 2004 Page(s):216 - 221
Summary: This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and.....
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46. Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
Mei, B.; Vernalde, S.; Verkest, D.; Lauwereins, R.; Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 2, 16-20 Feb. 2004 Page(s):1224 - 1229 Vol.2 Digital Object Identifier 10.1109/DATE.2004.1269063
Summary: Coarse-grained reconfigurable architectures have seen growing importance recently. Design tools and methodology are essential to their success. Based on our previous work on modulo scheduling algorithms and a novel architecture with tightly coupled V.....
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47. X4CP32: a coarse grain general purpose reconfigurable microprocessor
Soares, R.; Azevedo, A.; Silva, I.S.; Parallel and Distributed Processing Symposium, 2003. Proceedings. International 22-26 April 2003 Page(s):8 pp. Digital Object Identifier 10.1109/IPDPS.2003.1213315
Summary: The X4CP32 is a novel coarse RPU runtime-reconfigurable general purpose microprocessor. It consists of 3 programming levels, based on a hierarchical array of easily and quickly reconfigurable entities. It brings a new concept of runtime reconfigurati.....
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